In the manufacturing of semiconductor devices, vias are often used to interconnect back-side and front-side metallization layers. For instance, radio frequency and power devices (e.g., High Electron Mobility Transistors (HEMTs), Field Effect Transistors (FETs), Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), or Schottky diodes) are fabricated on a semiconductor wafer that may include front-side metallization as well as back-side metallization. The front-side metallization and the back-side metallization are interconnected by vias that extend from the back-side metallization to the front-side metallization. For example, a HEMT may include front-side metallization for source and drain contacts of the HEMT as well as back-side metallization that is interconnected to the front-side metallization by corresponding vias. In this case, the back-side metallization is desired to carry large currents to and from the source and drain of the HEMT.
One issue that arises is that, after dicing of the semiconductor wafer, solder used to mechanically and electrically connect the resulting die to a mounting substrate (e.g., a laminate) during packaging of the die mixes with the back-side metallization. As a result of the mixing, metal (e.g., Tin) from the solder moves through the back-side metallization and can destroy the die. In particular, any solder (e.g., AuSn, AuMo, or the like) that breaches through the back-side and front-side barriers creates a path for the solder to migrate through and degrade the front-side Schottky contact. For example, if the back-side metallization is Gold and the solder is Gold-Tin, the Gold-Tin solder mixes with the Gold back-side metallization. The Tin from the Gold-Tin solder then moves through the Gold back-side metallization and degrades the front-side Schottky contact.
To help prevent the mixing of the solder and the back-side metallization, a thick layer (e.g., a 1 micron thick layer) of Titanium or similar metal is typically deposited over the back-side metallization. However, depositing this thick layer takes a significant amount of time. The wafer may be impacted by the heat to which it is exposed while depositing this thick layer (e.g., a bonded carrier/substrate interface may be impacted by the heat). In addition, a significant amount of stress is created by this metal deposition.